Variable breakdown storage cell with negative resistance operating characteristic

ABSTRACT

This application discloses a storage cell which employs a single gated multi-emitter semiconductor device that exhibits a negative resistance operating characteristic. The semiconductor device is biased to have two stable operating states on this negative resistance characteristic and is addressed by a word line connected to one of its emitters and a bit line connected to the other of its emitters. A parasitic transistor is formed by the two emitters and the gating layer of the semiconductor device. By application of half-select pulses to the word and bit lines, the parasitic transistor is broken down to cause a temporary current flow in the gating region of the semiconductor device. While this current flows in the gating region, the operating characteristic of the semiconductor device is changed so that there is only one stable operating state for the semiconductor device. The operation of the semiconductor device therefore shifts to this single operating state. When the temporary current flow ends the semiconductor device will be in a low voltage, high current stable state along the negative resistance characteristic irrespective of the operating state of the semiconductor device prior to the application of the half select pulses. When such a storage cell is manufactured in monolithic form, very high cell densities and extremely high operating speeds are obtainable.

United States Patent Davidson et al.

[451 May 2, 1972 [54] VARIABLE BREAKDOWN STORAGE CELL WITH NEGATIVERESISTANCE OPERATING CHARACTERISTIC [72] Inventors: Evan E. Davidson,Wappingers Falls;

Richard L. Moore, Liverpool, both of [73] Assignee: InternationalBusiness Machines Corporation, Armonk, NY.

[22] Filed: Dec. 15, 1969 [21] Appl. No: 885,152

[52] U.S. CI. ..340/173 NR, 307/252 R, 307/289,

307/299, 317/235 AB, 340/173 FF [51] Int. Cl. ..Gllc 1l/40, I-I03k 17/24[58] Field of Search... ....340/173 NR, 173 LS, 173 PP,

340/173 PE; 307/252 R, 289, 299A; 317/235 UA, 235 AB [56] ReferencesCited UNITED STATES PATENTS v 3,218,613 11/1965 Gribble ..340/173 PE3,261,985 7/1966 Somos ..317/235 OTHER PUBLICATIONS Davidson, DualEmitter Avalanche Transistor Memory Array,

Schuenemann, Storage Natrix, IBM Tech. Disc. Bul., Vol. 1 1 No. 5,10/68, 340/173 State, pp.443-

Primary E.\'aminerStanley M. Urynowicz, Jr. Assistant E.\'aminerStuartHecker Att0rneyl-lanifin and Jancin and James E. Murray [5 7] ABSTRACTThis application discloses a storage cell which employs a single gatedmulti-emitter semiconductor device that exhibits a negative resistanceoperating characteristic. The semiconductor device is biased to have twostable operating states on this negative resistance characteristic andis addressed by a word line connected to one of its emitters and a bitline connected to the other of its emitters. A parasitic transistor isformed by the two emitters and the gating layer of the semiconductordevice. By application of half-select pulses to the word and bit lines,the parasitic transistor is broken down to cause a temporary currentflow in the gating region of the semiconductor device. While thiscurrent flows in the gating region, the operating characteristic of thesemiconductor device is changed so that there is only one stableoperating state for the semiconductor device. The operation of thesemiconductor device therefore shifts to this single operating state.When the temporary current flow ends the semiconductor device will be ina low voltage, high current stable state along the negative resistancecharacteristic irrespective of the operating state of the semiconductordevice prior to the application of the half select pulses. When such astorage cell is manufactured in monolithic form, very high celldensities and extremely high operating speeds are obtainable.

4 Claims, 7 Drawing Figures PATENTEDMAY 2:912

VCEPT W SHE? 1 OF 3 VCE sus FIGJ CE MAX VCE ZN o

INVENTORS EVAN E. DAVIDSON MOHARD L. MOORE BYVZv ATTORNEY P-SUBSTRATEREAD FIG.7

VARIABLE BREAKDOWN STORAGE CELL NEGATIVE RESISTANCE OPERATINGCHARACTERISTIC BACKGROUND OF THE INVENTION This invention relates tobi-stable circuits and more particularly to storage cells applicable foruse in monolithic memorles.

Three characteristics are very desirable in monolithic memory arrays.One of these characteristics is a high cell density on the monolithicchips making up the memory array. Another desirable characteristic ofsuch monolithic memories is that they operate very fast, or, moreexplicitly, that the information stored in the storage cells of thememory be rapidly read out and new data written into the cells at highspeed. A final characteristic desirable in monolithic memories is thatthe power dissipated by the storage cells of the memory be small, or inother words, heat generated in the storage cells by operation of thememory be minimal.

SUMMARY OF THE INVENTION In accordance with the present invention, astorage cell for a monolithic memory is provided which requires verylittle area when formed on a monolithic chip, can be rapidly accessedfor reading and writing and dissipates very little power during theoperation of the memory. This storage cell comprises a single gatedmulti-emitter semiconductor device which exhibits an operatingcharacteristic that is changeable by the application of current to thegating region of the device. This semiconductor device is normallybiased so that it has two stable operating states along a negativeresistance operating characteristic. The cell is accessed by a word lineconnected to one of the emitters and a bit line connected to the otherof the emitters. When concurrent half-select pulses are applied to theword and bit lines, a parasitic transistor formed between the twoemitters of the semiconductor device and including the gating region ofthe semiconductor device is broken down and current temporarily flowsthrough the gating region. This current causes a change in theoperatingcharacteristic of the semiconductor device so that the semiconductordevice has only one stable operating state. The operation of thesemiconductor device then switches to the one stable operating state andwhen the temporary current flow ends the semiconductor device will be ina low voltage high current stable state along the negative resistancecharacteristic irrespective of the operating state of the semiconductordevice prior to the application of the half-select pulses.

Therefore, it is an object of this invention to provide a storage cellwhich takes up very little space on the monolithic chip.

A second object of the invention is to provide a storage cell which canbe rapidly accessed for reading and/or writing.

A third object of the invention is to provide a storage cell whichdissipates very little energy.

Another object of the invention is to provide a storage cell whichoperates on the negative resistive characteristic of the singlesemiconductor device.

DESCRIPTION OF THE DRAWING These and other objects, features andadvantages of the invention will be apparent from the following moreparticular description of a preferred embodiment of the invention asillustrated in the accompanying drawings of which:

FIG. 1 is a graph showing how the'operating characteristic of atransistor varies as a function of base current.

FIG. 2 is a schematic of a monolithic memory array fabricated inaccordance with the present invention.

FIG. 3 is a graph of potentials employed in accessing the storage cellof FIG. 2.

FIG. 4 is a plan view of one monolithic form of the present invention.

FIG. 5 is a sectional view taken along line 55 of FIG. 4.

FIG. 6 is a schematic of a second storage cell employing the presentinvention.

FIG. 7 is a graph of the potentials used to access the storage cell ofFIG. 6 for reading and writing.

FIG. 1 illustrates the grounded emitter characteristics of a bi-polartransistor. The three curves l0, l2 and 14 show the change in collectorcurrent with variation of collector to emitter voltages of threedifferent base currents. Use of a positive base current results in thelinear operating curve 14. However, as base current is reduced to Zeroand goes negative, a negative resistance region occurs as shown incurves l0 and 12 in which the peak collector to emitter voltage Vincreases with more negative base current until the curve 10 is reachedwhere a base to emitter punch-through occurs. After thispunch-through'occurs, any further increase in negative base vbias doesnot create further increase in collector to emitter potentials.

By properly placing a load line 16 on the negative resistancecharacteristic 10, a two state memory cell can be devised. Such a cellis shown in FIG. 2 as the memory cells 18 in a monolithic array accessedby word write lines X through X word read lines Z, through 2,, and bitlines Y, through Y,,,. Each of the cells 18 contains a multi-emittertransistor 20 with its collector connected to a word read line and oneemitter connected to aword write line and the other emitter coupled to abit line. The emitter E is connected directly to the bit line Y, whilethe emitter E is. connected through the load resistance R to the wordwrite line X Connected between the emitters El and E2 is biasing circuitfor biasing the base B of the transistor 20. This biasingcircuitconsists of two back-toback diodes D1 and D2 between emitters E1 and E2and a resistance R2 joining the common terminals D1 and D2 to the baseB. The transistor 20 is biased for bi-stable operation along itsnegative resistance characteristic 10 by the potential +V, theresistance R1 and negative base current supplied through the describedbiasing circuit so that there exists two stable operating statesreferred to as the 0 and l states in FIG. 1.

While the storage cell 18 is storing information, the X, word line ismaintained at ground potential while the Y,, bit line is maintained at apotential +V2 above ground causing emitter E1 to conduct and emitter E2to be back biased. This assures that the storage cell 18 will be ineither the l or O operating states shown in FIG. 1 since the currentwill flow from the collector terminal through emitter terminal E1 andthe load resistance Rl to the X word line. The potential difference V-V2between the collector and the emitter E2 of transistor 20 is below V forthe transistor 20. Thus if conduction were to occur through emitter E2it would be insufficient to sustain the transistor 20 in its l stablestate.

Assume now that a 1 is to be written into the cell and that the storagecell is initially in the 0 operating state. Then, the potential on the Xword line is raised to +VI while potential on the Y bit line is reducedto V3. This causes temporary conduction to occur between emitters E1 andE2 as a result of break-down in a lateral parasitic transistorconsisting of emitter regions E1 and E2 and the base region B. When thistemporary conduction occurs, positive current flows in the base Bcancelling the negative current flowing through the base and resistorR2. The operation of transistor 20 then switches from curve 10 to curve14 in FIG. 1 so that the transistor 20 is no longer stable at the 0point on the load line 16. Therefore, conduction shifts to point A onthe curve, the only stable point on the load line 16.

After the coincident half-select voltages subside to their quiescentvalues, the operation of the transistor 20 returns to curve 10. The cellthen operates at the l operating state on curve 10 since the potential Vis sufficient to exceed the minimum potential VCEPT along the load line.Therefore the cell stores a 1. If the cell has been initially in its loperating state it would have remained there after the word line and bitline were driven by the +Vl and -V3 half-select coincident pulses shownin FIG. 3.

Assume now that a 1 is stored in the storage cell 18 and it is desirableto write a 0 into the storage cell. Then the X, word line is pulsed witha +V1 voltage. This reduces the collector current Ic flow throughtransistor 20 below the current ,-length of the channel 26 with an 'N+arsenic diffusion. An

on the URI load line. If the transistor 20 had been operating at thepoint on the load line 16 when the write 0 pulses were applied to the Xword line it would still be operating there after the write 0" pulsesend.

Therefore it can be seen that the transistor 20 has two stable statesand can be switched between the two stable states at will by half-selectpotentials applied to the emitters El and E2. For this reason, binarydata can be stored in any location 0,0 to M,N of the memory by theproper selection of one of the bit lines Y., to Y,,, and one of the wordlines X, to X,,,.

Data can be read out of the storage cell by raising the potential on the2,, word read line sufficiently to cause both emitters El and E2 toconduct. If a f l is stored in the cell, the collector currentconduction through transistor 20 is heavy. This heavy conduction oftransistor 20, which during read passes through resistor R produce alarge read pulse 22 on the Y, bit line that can be sensed by a senseamplifier. If a 0 is stored in the storage cell, significantly lesscurrent passes through the transistor 20 so that during read time thiscurrent produces a significantly smaller voltage 24 across resistor RThe difference in magnitude between the pulses 22 and 24 is easilydetected by sense amplifier. Since operation of the transistor duringreadout is in the avalanche mode very rapid charging of the 2,, linecapacitances occur and therefore short readout times are accomplished.

Due to the fact that resistance R1 is not in the readout path when datain the storage cell is being read, the resistance R] may be selectedwith respect to the sense resistance R, so as to provide bi-levelpowering ofthe storage cell. The resistor R is selected to besignificantly larger than the resistor R Therefore considerably lesscurrent flows through resistor R than resistor R, while information isbeing read 'out of the storage cell. This provides a large read signalwhile at the same time reduces power consumption of the storage cellwhile the cell is not being accessed. I

As we mentioned previously, a bias network consisting of diodes'Dl andD2 and resistor R2'is connected between the emitters El and E2 and thebase, of transistor 20. The purpose of the circuit is to leak charge offthe base B of the transistor 20. This leakage current is the negativecurrent that biases transistor 20 on negative resistance curve 10.Furthermore, the leakage current prevents charges from building upacross the base to collector capacitance C to cause the transistor 20 toswitch states in response to noise signals on the word and bit lines.The diodesDl and D2 are included in the circuit to prevent positivecurrent flow into the base through resistor R2. These diodes D1 and D2are backbiased by addressing pulses on the word and bit lines. A halfselect signal will not trigger a change in state of the cell 18. In theforward bias direction the voltage drop across diodes D1 and D2 isselected to be about 0.4 volts as compared to the base to emitter dropof about 0.7 volts for the transistor 20. This assures that the voltagedrops across resistor R2 and diodes D1 and D2 produced by the leakingbase charge will not cause the base to emitter junctions of transistor20 to conduct andtherefore cause spurious signals. v

The diodes DI and D2 can be fabricated as Schottky diodes 24 in themonolithic form of the cell shown in FIGS. 4 and 5. As shown in thosefigures a channel 26 of N+ type material is formed by diffusion in a Pepitaxial layer 28 grown on a P- type substrate 30. In this channel 26all the storage cells on one word line are formed. Parallel channels 26aand 26b contain the storage cells of other word lines of the memory.

The fabrication of the storage cells is accomplished by first diffusinga subchannel 32 into the substrate 30 along the The phosphorous diffusesfaster than the arsenic producing the dogbone cross section in FIG. 5. Afinal N+ phosphorous diffusion is now made This final diffusioncompletes the col lector areas of the transistor. For each transistor20, there is a larger 36 and smaller 38 region of P EPI material in theN channel 26. In the larger region 36, two emitter areas 40 and 42 and adumbell resistance strip 44are diffused with this final diffusion. Whilethe final diifusion into the small P region 38 produces a dumbellresistance strip 46 and two contact areas 48 and 50. The metal Schottkydiodes 24 are then placed on the larger P region 30 and appropriatemetallization connections 50 are placed between the various difiusionsto the bit and word lines. The smaller P region 30 then serves asresistance R1 while the Schottky barrier diode serves as diodes D1 andD2 and the dumbell resistance between sections of the large P diffusionserves as resistance R2.

Up to now we have discussed the invention as it applies to a transistor20. The invention can also be used using a silicon control rectifier 48as shown in FIG. 6. This cell is accessed by reading and writingpotentials as illustrated in FIG. 7. The cell is more completelydescribed in copending application, Ser. No. 885,153 filed on even dateherewith (Dec. 15, 1969).

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is:

1. In a memory with storage cells addressed by word and bit lines, theimprovement comprisinga new storage cell includmg:

a multi-emitter gated semiconductor device exhibiting an operatingcharacteristic changeable by theapplication of current to the gatingregion of the device and having emitter regions in the gating region sothat the emitter regions with the gating region form a transistor, oneof said emitter regions being coupled to a word line and another emitterregion being coupled to a bit line; 7

load means for biasing said semiconductor device so'that thesemiconductor device operates along-a negative resistance operatingcharacteristic of said device and has two stable operating states alongsaid negative resistance operating characteristic, the first state ahigh voltage low current state andthe second state a low voltage highcurrent state;

bias means for coupling the base of said multi-emitter gatedsemiconductor device to the emitters of said semiconductor device so asto bias the semiconductor device to operate on said negative resistancecharacteristic, and;

means for application of half-select pulses to both the word line andbit line which upon simultaneous application to the emitters of saidsemiconductor devices causes conduction of said transistor fromemitter-to-emitter to inject current into the gating region of thesemiconductor device to temporarily change the operation of saidsemiconductor device from said negative resistance .characteristic to asecond operating characteristic so that the semiconductor device isswitched from the'first stable state to the second stable'state whenoperation of the semiconductor device returns to operation along saidnegative resistance operating characteristic at the end of thehalf-select pulses.

2. The storage cell of claim 1 wherein said multi-emitter semiconductordevice is a multi-ernitter transistor.

3. The storage cell of claim 2 wherein said bias means is aunidirectional current path means for discharging the basecollectorjunction of the multi-emittcr transistor.

- 3,660,822 4. The storage cell of claim 3 said unidirectional currentpath means comprises two diodes coupled back to back between saidemitters and resistor coupling the common terminals of the back to backdiodes to the base of the transistor.

1. In a memory with storage cells addressed by word and bit lines, theimprovement comprising a new storage cell including: a multi-emittergated semiconductor device exhibiting an operating characteristicchangeable by the application of current to the gating region of thedevice and having emitter regions in the gating region so that theemitter regions with the gating region form a transistor, one of saidemitter regions being coupled to a word line and another emitter regionbeing coupled to a bit line; load means for biasing said semiconductordevice so that the semiconductor device operates along a negativeresistance operating characteristic of said device and has two stableoperating states along said negative resistance operatingcharacteristic, the first state a high voltage low current state and thesecond state a low voltage high current state; bias means for couplingthe base of said multi-emitter gated semiconductor device to theemitters of said semiconductor device so as to bias the semiconductordevice to operate on said negative resistance characteristic, and; meansfor application of half-select pulses to both the word line and bit linewhich upon simultaneous application to the emitters of saidsemiconductor devices causes conduction of said transistor fromemitter-to-emitter to inject current into the gating region of thesemiconductor device to temporarily change the operation of saidsemiconductor device from said negative resistance characteristic to asecond operating characteristic so that the semiconductor device isswitched from the first stable state to the second stable state whenoperation of the semiconductor device returns to operation along saidnegative resistance operating characteristic at the end of thehalf-select pulses.
 2. The storage cell of claim 1 wherein saidmulti-emitter semiconductor device is a multi-emitter transistor.
 3. Thestorage cell of claim 2 wherein said bias means is a unidirectionalcurrent path means for discharging the base-collector junction of themulti-emitter transistOr.
 4. The storage cell of claim 3 saidunidirectional current path means comprises two diodes coupled back toback between said emitters and resistor coupling the common terminals ofthe back to back diodes to the base of the transistor.